Flip-flop & D Flip-flop

A D flip-flop is literally a D Latch with a clock input dependency. A D latch is a combination logic element while a D flip flop is a synchronous logic element. D latch is a synchronous logic element i.e. it requires clock signal to operate. Without a clock signal, a synchronous logic will not change state or even respond to change in input.

D Flip-flop is the direct upgrade of the D Latch. D flip-flop has all the advantages of D latch but none of the drawbacks. Theoretical D flip-flop has just 2 states, SET and RESET and no invalid state. A clock signal is required to change the output states as all flip-flop are synchronous device. Practical flip-flops have two extra inputs called ” Set ” and ” Reset “. Input ” Set ” is also known as Preset, which is used to set the user defined states on the flip-flop. User defined states are achieved by applying the condition on the D input. Reset input is used to bring the flip-flop to its initial condition. Both Set and Reset input are asynchronous. Shift Registers are one of the main application of a D F/F. Learn about shift registers in this blog-post.